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STP40NF12
N-CHANNEL 120V - 0.028 - 40A TO-220 LOW GATE CHARGE STripFETTM II POWER MOSFET
TYPE STP40NF12
s s s s
VDSS 120 V
RDS(on) < 0.032
ID 40 A
TYPICAL RDS(on) = 0.028 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION TO-220
3 1 2
DESCRIPTION This Power MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer application. It is also intended for any application with low gate charge drive requirements.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS HIGH-EFFICIENCY DC-DC CONVERTERS s UPS AND MOTOR CONTROL
s
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM ( ) PTOT dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Operating Junction Temperature Value 120 120 20 40 28 160 150 1 14 150 - 55 to 175
(1) ISD 40A, di/dt 600A/s, VDD V(BR)DSS, Tj T JMAX. (2) Starting Tj = 25C, ID = 40A, VDD = 50V
Unit V V V A A A W W/C V/ns mJ C
(q) Pulse width limited by safe operating area
October 2003
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THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1 62.5 300 C/W C/W C
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V Min. 120 1 10 100 Typ. Max. Unit V A A nA
ON (1)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10V, ID = 20 A Min. 2 Typ. 2.8 0.028 Max. 4 0.032 Unit V
DYNAMIC
Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 25V, ID = 20 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 40 1880 265 110 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 50 V, ID = 20 A RG = 4.7 VGS = 10V (see test circuit, Figure 3) VDD = 80V, ID =40A,VGS = 10V Min. Typ. 28 63 60 11 21 80 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol td(off) tf Parameter Turn-off-Delay Time Fall Time Test Conditions VDD = 50 V, ID = 20 A, RG = 4.7, VGS = 10V (see test circuit, Figure 3) Min. Typ. 84 28 Max. Unit ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, VGS = 0 ISD = 40 A, di/dt = 100A/s, VDD = 25V, Tj = 150C (see test circuit, Figure 5) 114 456 8 Test Conditions Min. Typ. Max. 40 160 1.3 Unit A A V ns nC A
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
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Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Drain-Source Breakdown vs Temperature
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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TO-220 MECHANICAL DATA
mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154
DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 oP Q
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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